1. Technical Field
This invention relates to a data processing device.
2. Related Art
Reconfigurable circuits (also called programmable logic circuits) of a PLD (Programmable Logic Device), an FPGA (Field Programmable Gate Array), etc., whose internal logic circuit configuration can be reconfigured (changed) become widespread. Generally, the internal logic circuit configuration of the PLD or the FPGA is set at the circuit starting time, but a device whose logic circuit configuration can be changed during the operation of the circuit is also developed. In recent years, use of a dynamically reconfigurable processor (DRP) whose internal logic circuit configuration can be reconfigured at high speed (for example, in one clock cycle) has also advanced.
The logic circuit configuration reconfigured on a reconfigurable circuit is called configuration. In a system using a reconfigurable circuit, generally, the configuration of the reconfigurable circuit is rewritten in order, whereby a circuit of a scale that cannot be configured on the reconfigurable circuit at a time can be implemented using the reconfigurable circuit.
In the system using the reconfigurable circuit, generally the reconfigurable circuit is often used under the control of a general-purpose CPU. A combination of software processing of a part of a processing sequence by a CPU and hardware processing of another part by a reconfigurable circuit is often conducted. Hitherto, in such a system, generally each of the CPU and the reconfigurable circuit has been provided with dedicated memory and data being processed by each of the CPU and the reconfigurable circuit has been read from and written to their respective memories.
In contrast to the conventional implementation system, it is considered that work memory of the CPU and the reconfigurable circuit is made common, whereby the memory cost is reduced and device is installed in an existing ASCI, etc., as IP core, whereby the device cost is reduced and the board occupation area is also decreased. In this case, however, it is necessary to note the relationship among bandwidths of the CPU, the reconfigurable circuit, and the memory. For example, to use the reconfigurable circuit (particularly, DRP) for image processing such as processing of a bit map image in print, handled image data is large and thus the input/output bandwidth of the reconfigurable circuit occupies the memory bandwidth and the memory band assigned to the CPU (and its peripheral devices) cannot be assigned.
In contrast, for example, it is also considered that an internal buffer of a small capacity is created on a chip on which a reconfigurable circuit is mounted and the processing result of the configuration formed on the reconfigurable circuit is passed to the next configuration through the internal buffer, whereby the memory band used by the reconfigurable circuit is decreased. To use the internal buffer of the small capacity, the data to be processed needs to be separated for each amount responsive to the capacity of the buffer for processing. In window processing of reading data of one window width with one data point (for example, pixel) as the reference to calculate the data point, for example, like filtering of an image, it is necessary to read extra data as much as the window width at both ends of the range of the data to be processed. Thus, to separate the data to be processed in a comparatively small amount at a time and read the data into the internal buffer, the relative rate of the window width to the amount of the data to be processed becomes high, resulting in degradation of the processing performance (processing efficiency). For example, filtering using a filter of 11×11 pixels is applied to a 33-line image read from the internal buffer, only 23-line image is obtained as the processing result and the processing efficiency becomes 23/33=about 70%.